Low-power transmission system

ABSTRACT

An efficient method and transceiver architecture combines elements to enable and facilitate the low power operation of a communications device; the combination of design elements, features, and functionalities are efficiently distributed among RF, APE, and baseband modules in order to exploit opportunities that can serve the goal of low or ultra low power consumption.

REFERENCE TO RELATED APPLICATIONS

This application is a divisional of and claims the benefit of U.S.patent application Ser. No. 13/156,105 filed Jun. 8, 2011, and which isincorporated herein by reference in as entirety,

TECHNICAL FIELD

The present invention relates generally to communication networks, andmore particularly, some embodiments relate to low-power receiverssuitable for implantable medical devices.

DESCRIPTION OF THE RELATED ART

With the many continued advancements in communications technology, moreand more devices are being introduced in both the consumer andcommercial sectors with advanced communications capabilities.Additionally, advances in processing power and low-power consumptiontechnologies, as well as advances in data coding techniques have led tothe proliferation of wired and wireless communications capabilities on amore widespread basis.

For example, communication networks, both wired and wireless, are nowcommonplace in many home and office environments. Such networks allowvarious heretofore independent devices to share data and otherinformation to enhance productivity or simply to improve theirconvenience to the user. Exemplary networks include the Bluetooth®communications network and various IEEE standards-based networks such as802.11 and 802.16 communications networks, to name a few.

Medical device makers, recognizing benefits of wireless technology,sought to include wireless communication capability with implantablemedical devices. Previous generation communication protocols forimplantable devices relied on inductive communications to transferinformation to and from the implanted device. Advances in low powerwireless communications enabled communications without reliance on theclose proximities required for communication via inductive links.Accordingly contemporary devices include a wireless transceiver at thedevice that communicates with a local wireless relay point or accesspoint. The local wireless relay point can be configured to log data fromthe implantable device and transfer that data to a base station, such asat a health care provider facility, personal computing device or otherbase station. The relay point can, for example, he incorporated into abracelet or other ‘wearable’ external device. Accordingly, the relaypoint can be provided with data storage devices, is user interface, andvarious communication links for communications to the base station.

In 1999 the Federal Communication Commission (FCC) standardized thecommunication protocols for medical device implants. The Medical DeviceRadiocommunications Service (MedRadio) is an ultra-low power,unlicensed, mobile radio service for transmitting data in support ofdiagnostic or therapeutic functions associated with implanted andbody-worn medical devices. The Medical Implant Communication Service(MICS) is a specification that governs such wireless communications withmedical implants.

A wireless system for implantable medical device(s) comprises at leastone implanted medical device (IMD) and an external communication device(ECD). The IMD (e.g., ICD, glucose monitor) is typically tasked withmonitoring and treating physiological conditions within the human body.The ECD can be a device that is capable of communicating both with theimplant and with a second device, perhaps using a different wirelesssystem.

The combination of transmit and receive functions defines a transceiver,and must thereby be designed with the goal of keeping the powerconsumption of the implantable device as low as possible. This includes,but is not limited to, the design of the communication link, the RF andanalog front-end (AFE) design, component modules and features, and theefficient use of sleep mode(s) that reduce, as much as possible, thetime when (at least) the implantable device is active. An RF design withlow-IF architecture allows a trade-off between receiver sensitivity andpower consumption in the analog stages. If symmetric link designs aresought after (with respect to the transmit and receive modules) thenboth devices would exhibit similarly low or ultra low power consumption,while being programmable to perform both roles.

The overall power consumption exhibited by the transceiver is furtherinfluenced by factors such as protocol, regulations, device discoveryand wake-up from sleep mode(s).

The operation of an IMD and ECD pair is governed by local regulations,and this includes the maximum transmission power, as well as the actionstaken to initiate communication.

In one aspect, FCC regulations in US require that the ECD perform theclear channel assessment (CCA). While in other areas the IMD can send aperiodic beacon, this is not the case in US.

According to FCC regulations, the ECD must monitor a MICS band channelfor at least 10 ms; it may use the first unoccupied one (may use best ifall occupied); the ECD must have monitored the channel it decides to useduring the past 5 sec. ECD may send some control information (e.g., aflag bit indicating whether the ECD has data to send, along with channelindex info bits) on some channel, for the IMD to use—should the ECD havedata to send.

The IMD must do all that is necessary to respond to the ECD and receiveany relevant control information in a manner that keeps powerconsumption as low as possible; this functionality may be assigned to aultra low power wake-up service or module.

In the worst case, the IMD must sequentially search through the tenchannels in order to receive the control message (information element)from the ECD; the design must aim to optimize the power consumed by theIMD while performing these functions.

BRIEF SUMMARY OF EMBODIMENTS OF THE INVENTION

Various embodiments of the invention provide an efficient method andtransceiver architecture that combines elements to enable and facilitatethe low power operation of the implantable device; the combination ofdesign elements, features, and functionalities are efficientlydistributed among RF, AFE, and baseband modules in order to exploitopportunities that can serve the goal of low or ultra low powerconsumption.

Other features and aspects of the invention will become apparent fromthe following detailed description, taken in conjunction with theaccompanying drawings, which illustrate, by way of example, the featuresin accordance with embodiments of the invention. The summary is notintended to limit the scope of the invention, which is defined solely bythe claims attached hereto.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention, in accordance with one or more variousembodiments, is described in detail with reference to the followingfigures. The drawings are provided for purposes of illustration only andmerely depict typical or example embodiments of the invention. Thesedrawings are provided to facilitate the reader's understanding of theinvention and shall not be considered limiting of the breadth, scope, orapplicability of the invention. It should be noted that for clarity andease of illustration these drawings are not necessarily made to scale.

FIG. 1 illustrates a transmission process with an exemplary structure ororganization of a baseband packet for transmitting signals to bereceived by embodiments of the invention.

FIG. 2 illustrates a hybrid mixer and super-regenerative receiverimplemented in accordance with an embodiment of the invention.

FIG. 3 illustrates an exemplary digital receiver subsystem block diagramimplemented in accordance with an embodiment of the invention.

FIG. 4 illustrates a block diagram of a transmitter architecture forgeneration of a signal for a network environment for which particularembodiments are configured.

FIG. 5 illustrates a digital receiver subsystem implemented inaccordance with an embodiment of the invention.

FIG. 6 illustrates an embodiment of a preamble structure fortransmission with packets in the system described with respect to FIG.5.

FIG. 7 illustrates a process for packet detection timing recovery andfrequency offset estimation performed by a timing recovery module.

FIG. 8 depicts the signal processing, performed at the receiver in FIG.5 during delay correlation.

FIG. 9 illustrates an example configuration of a demodulator for adifferentially-coherent encoded M-PSK signal.

FIG. 10 illustrates for reducing the frequency of corrupted packets andpower saving at the decoder implemented in accordance with an embodimentof the invention.

FIG. 11 illustrates an example computing module that may be used inimplementing various features of embodiments of the invention.

The figures are not intended to be exhaustive or to limit the inventionto the precise form disclosed. It should be understood that theinvention can be practiced with modification and alteration, and thatthe invention be limited only by the claims and the equivalents thereof.

DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION

FIG. 1 illustrates a transmission process with an exemplary structure ororganization of a baseband packet for transmitting signals to bereceived by embodiments of the invention. Diagram 100 illustrates thestructure and organization of a digital subsystem for generating andtransmitting a physical layer convergence protocol (PLCP) packet header.PHY layer header information is concatenated 101 with a header checksum(HCS). As understood in the art, the PHY layer header information isused for communicating PHY layer information between PHY layers ofdevices in the network and the HCS is used for verification.

The concatenated data is encoded 102 at a forward error correcting (FEC)encoder. In the illustrated embodiment, the encoder 102 is u (31,19) BCHencoder. In further embodiments, other BCH encoders could be employed,or more generally other algebraic FEC codes or other FEC codes. Afterencoding 102, the codeword symbols are spread 103, interleaved 104, andscrambled 105 in a manner known in the art. The resultant bits aremapped 106 to output symbols using a symbol mapper. For example, thesymbol mapping 106 may output symbols for various modulation schemes,such as BPSK, DBPSK, double DBPSK,

${\frac{\pi}{2} - {DBPSK}},$

FQPSK, and SOQPSK. After mapping 106, the symbols are pulse shaped 107,for example suing a predetermined matched filter, such as au SRRCfilter. After pulse shaping 107, the bits are converted to analog at DAC108 and passed to an analog subsystem for transmission. In someimplementations, the DAC 108 may oversample the data to improvereception, for example at an 8× baud rate.

Diagram 110 illustrates the structure, and organization of a digitalsubsystem for generating a physical layer service data unit (PSDU). AMAC layer header, frame body, and frame checksum are concatenated 111 ina manner similar to the process described above with respect to the PLCPheader. The concatenated information is encoded at encoder 112. In theillustrated embodiment, the PLCP header is encoded using a (63, 15) BCHencoder. However, in further embodiments, other BCH encoders could beemployed, or more generally other algebraic FEC codes or other FECcodes.

As discussed above, after encoding, the bits are spread 113, interleaved114, and scrambled 115 to condition them for transmission in a mannerknown in the art. A symbol mapper 116 then maps the bits onto symbolsfor transmission. The symbol mapper 116 may employ the same modulationscheme used in the subsystem 100, or may employ another type ofmodulation scheme. For example, the symbol mapping 116 may outputsymbols for various modulation schemes, such as BPSK, DBPSK, doubleDBPSK,

${\frac{\pi}{2} - {DBPSK}},$

FQPSK and SOQPSK. After mapping 116, the symbols are pulse shaped 117,for example suing a predetermined matched filter, such as an SRRCfilter. After pulse shaping 117, the bits are converted to analog, atDAC 118 and passed to an analog subsystem for transmission. In someimplementations, the 118 may oversample the data to improve reception,for example at an 8× baud rate.

FIG. 2 illustrates a hybrid receiver that consists of LO IF receiver andsuper-regenerative receiver implemented in accordance with an embodimentof the invention. In some network environments, a relay point (such as amedical bracelet) is configured to establish a network link with tolow-power device (such as a medical implant). According to certainrestrictions, the medical implant may not be allowed to transmit channelselection information to the relay point. Rather, the relay point mustselect a communications channel from a band of channels and communicatethe choice of channel to the medical device. In one embodiment, therelay point communicates the channel choke by broadcasting a wake upsignal including the channel selection choice on the selected channel.The medical implant uses a wide-band detection method to monitor theentire band of channels, and thereby receives the wakeup signal.Subsequently, the low-power device is able to tune to the selectedchannel and for further communications. The wide-band reception usesless power than narrowband reception (which may require a sequentialscan of the channels to receive the channel selection and wakeupinformation). The illustrated example shows an analog reception systemwith a wideband reception subsystem for receiving wake-up signals and anarrowband reception subsystem for further communications. In somefurther embodiments, beacon communications can also be performed usingthe wide-band reception mode, to further save power.

In the illustrated example, input signal 206 is passed through a bandfilter 210. For an application for MIC, the input signal will be between402-405 MHz and the band fiber 210 comprises a MICS band filter. Thefiltered signal passes through a low-noise amplifier (LNA) 211 to eithera tunable narrow-band receiver 204 or the wideband receiver 203. Aswitch 209 controls this selection. Accordingly, in the illustratedembodiment, both receiver subsystems share the functionality of theantenna band filter 210 and LNA 211.

In the search or beacon reception mode, the selection switch 209 thatfollows the LNA 211 connects to the super-regenerative receiver block219. In the case of high data rate exchange or in the presence of astrong in-band interferer, the switch 209 selects higher powerconsumption low IF receiver 204. This adaptable architecture allows foroptimal solution in terms of power savings and robustness, both of whichare important for medical wireless application and other low-powerapplications.

The super-regenerative receiver 219 comprises an RF oscillator 223 and218 that is periodically “quenched” by a lower frequency waveform(provided by quench generator 231). When the quench signal is applied tothe oscillator 223 and 218, oscillations start to build up with anexponentially growing envelope. Applying an external signal at theoscillator's nominal frequency speeds the growth of the envelope ofthese oscillations (provided by VCO 223). In low-power simplelogarithmic mode of operation is utilized in order to limit oscillationamplitude. Thus, the duty cycle of the oscillation changes in proportionto the amplitude of the applied RF signal (from LNA 211).

Super-regenerative detector 219 is well suited for OOK (on/off-keyed)signaling detection, which, in some embodiments, is used for wake-up,channel selection, or beaconing information. In other embodiment, thewakeup signal may comprise an un-modulated carrier burst. Thesuper-regenerative detector 219 constitutes a sampled-data system; thatis, each quench period samples and amplifies the RF signal (from LNA211). To reconstruct the original modulation, in asynchronous mode ofoperation the quench generator 213 operates at a frequency a few timeshigher than the highest frequency in the original modulating signal. Thesuper-regenerative receiver 219 exhibits high sensitivity and lowselectivity. Although super-regenerative receivers tend to radiate RFenergy through the antenna during oscillation period, this effect isprevented by LNA 211.

The super-regenerative receiver 219 comprises a voltage controlledoscillator (223). In the illustrated embodiment, the channel bandcomprises between 402 and 405 MHz, so a ˜400 MHz VCO is used in aparticular embodiment, a 403.35 MHz VCO is employed). Typical on-chipinductance for a 400 MHz oscillator is large and low-Q. Accordingly, inthis embodiment, an external inductor 218 is employed in conjunctionwith VCO 223.

A PLL frequency synthesizer 227 provides the external signal at theVCO's nominal frequency. In one embodiment, the PLL 227 is sharedbetween the super-regenerative receiver 219 and mixer IF receiver 204,and an appropriate switchblade N-registers divider is used to providethe subsystems with the appropriate frequency signals. The reference PLLclock is derived from a crystal 229 controller reference oscillator 226.

The receiver 219 further comprises a conventional envelope detector 225and level comparator 228. A controller 221 provides a control frequency234 for the PLL 227, a control frequency 230 fro the quench generator231. In embodiments using modulated signals for wake-up, channelselection, or beaconing, the controller 221 may further providedemodulation of the received signals. In these embodiments, thecontroller 221 directly outputs a clock signal 222 and the demodulateddata 224 for use by the MAC layer. The controller 221 may furtherprovide clock restoration functionality and may provide asuper-regenerative receiver resynchronization signal 232.

The narrow-band receiver subsystem 204 comprises a tunable low IF mixerreceiver subsystem. Mixers and rotators 205 and 213 implement animage-reject mixer with the receiver reference signal 216. The signal216 is output by PLL 227, using the VCO 217. In one embodiment the VCO's217 characteristics may be chosen according to the particularapplication. For example, in a particular embodiment, the VCO 217comprises a 1.6 GHz VCO and the reference signal 216 is generated usinga divider 220.

The receiver subsystem 204 further comprises a bandpass filter 208configured to pass as frequency band at a low intermediate frequency(IF). The receiver subsystem 204 further comprises a conventionallimiting amplifier 207 coupled to the filter 208. In the illustratedembodiment, digital conversion is implemented using a single bit ADC 212or “slicer.” The operation of the single bit ADC is discussed in furtherdetail below.

In further embodiments, the low-power device comprises a transceiver,and some of the illustrated components are used for transmission aswell. For example, the reference clock 226 with crystal 229), PLL 227,VCO 217, and divider 220 (if used) may be used to output a localoscillator frequency signal 215 for the transmitter.

In some embodiments, if the controller 221 detects sufficientinterference on the channel band, such that reception of the wakeupsignal, beaconing information, or channel selection information, the MAClayer utilize the receiver subsystem 204 for any or all of thesefunctions. For example, the receiver subsystem 204 may be used tosequentially scan the available channels of the frequency band forincoming channel selection or beaconing information.

FIG. 3 illustrates an exemplary digital receiver subsystem block diagramimplemented in accordance with an embodiment of the invention. In theillustrated embodiment, an analog signal is received from the analogsubsystem 310. For example, the analog subsystem 310 may implemented asthe subsystem in FIG. 2, with the signal received from the low IF mixingsubsystem 204. The signal is converted to digital using ADC 306, whichin some embodiments may comprise a single bit ADC. The signal is thendigitally down convened from IF to baseband at digital down converter307. Down converter 307 may implemented as described below, or in anyother conventional manner. The IF may be equal to approximately the halfchannel spacing, and can avoid DC-offset and flicker noise issues thatmay otherwise result from direct conversion in the analog subsystem 310.

In environments where to pulse shaping filter is employed at thetransmitter, a matched filter 308 is used to filter undesirablecomponents and any additional signals that may arise from out of bandnoise or interference from other communications channels. The filteredsignal is provided to a signal-to-noise ratio (SNR) estimator 315 foruse in rate selection or other conventional link adaptations oradjustments of receiver variables. The filtered signal is furtherprovided to a timing and frequency estimation module 313 for use insample selecting, down sampling, and frequency correction in module 305.After the signal has been downsampled, and frequency correction, thesignal is demodulated at module 309, descrambled at module 311,deinterleaved at module 312, &spread at module 314, and finally decodedat module 316. These modules may all be implemented as discussed belowor in a conventional manner known to one of ordinary skill in the art.The decoded data is then provided to the MAC layer 317 for furtherprocessing and use.

FIG. 4 illustrates a block diagram of a transmitter architecture forgeneration of a signal for a network environment for which particularembodiments are configured. The RF signal in this system is

${x_{RF}(t)} = {{\sum\limits_{n}{{s_{R}\lbrack n\rbrack}{p_{T}\left( {t - {nT}_{b}} \right)}{\cos \left( {2\pi \; f_{0}t} \right)}}} - {{s_{t}\lbrack n\rbrack}{p_{T}\left( {t - {nT}_{b}} \right)}{\sin \left( {2\pi \; f_{0}t} \right)}}}$

where s[n]=S_(g)[n]+jS₁[n] is the baseband data symbols 404 and 408 onthe in-phase 403 and quadrature channels 413, respectively, p_(r)(t) ithe pulse shaping filter 406 (which is applied to both channelsseparately). T_(b) is the symbol/baud interval (which is produced byoversampling at modules 405 and 409), and f_(c) is the carrier frequency(which the signal is modulated to on at RF frontend 412). For a BANtransceiver operating in the MICS band, the center frequency f_(c) is inthe range of 402-405 MHz. The bandwidth of each channel in MICS band is300 KHz, which means

$T_{b} > {\frac{1}{{300K}\mspace{11mu}}\; {\sec.}}$

According to the BAN PHY specification, the pulse shaping filterp_(r)(t) is a square-root raised cosine (SRRC) filter (or RRC). Theseparameters may all be modified as applicable for different networkenvironments.

In the illustrated transmitter, the baseband signal s[n] 404 and 408,are oversampled 405 and 409 by a factor of L and sent over the I and Qchannels 405 and 409 separately. The SRRC 406 is used to shape thespectrum of transmitter signal. After SRRC filtering, the digital signalis then converted to analog signal via DACs 407 and 411. The resolutionof DAC has an impact to the shape of transmit spectrum and the overallperformance. In an alternative implementation, a single DAC may beemployed by modulating the baseband signal to a low-IF signal beforeDAC.

FIG. 5 illustrates a digital receiver subsystem implemented inaccordance with an embodiment of the invention. The illustratedembodiment is described in conjunction with the signal described withrespect to FIG. 4. Various modifications may be made to the modules andreceiver parameters for other implementations. The digital receiversubsystem receives a signal from an RF front end 513. In someembodiments, the RF front end 513 may comprise an analog receiversubsystem such as the one described with respect to FIG. 2, inparticular subsystem 204. In other embodiments, the RF front end 513 maycomprise a conventional analog receiver.

The RF sample 506 provided by the RF front end 513 is at a low-IF. Inthe illustrated embodiment, the low-IF signal is described as:

${y_{IF}(t)} = {{\sum\limits_{R}{{S_{R}\lbrack n\rbrack}{p_{T}\left( {t - {nT}_{b}} \right)}{\cos \left( {2\pi \; f_{IF}t} \right)}}} - {{s_{1}\lbrack n\rbrack}{p_{T}\left( {t - {nT}_{b}} \right)}{\sin \left( {2\pi \; f_{IF}t} \right)}} + {w(t)}}$

where f_(IF) is the tow IF frequency. An ADC 514 samples the data toprovide a sampled signal. In one embodiment, the rate of the samplestaken by ADC is assumed to be L times faster than the symbol rate R,where L is the oversampling rate used in the transmission as describedabove. In the particular illustrated embodiment the IF (f_(IF)) isselected such that L*R=4f_(IF).

The in-band and quadrature components of the signal are converted tobaseband using mixers 509 and 520. Mixer 509 multiplies the signaly_(IF)[n] by

${\cos \left( {2\pi \; f_{IF}\frac{T_{b}}{L}n} \right)}.$

Mixer 520 multipliers the signal by

$- {{\sin \left( {2\pi \; f_{IF}\frac{T_{b}}{L}n} \right)}.}$

In some embodiments, computation of the mixers 509 and 520 is reduced byselecting f_(IF) such that

${{\cos \left( {2\pi \; f_{IF}\frac{T_{b}}{L}n} \right)}\mspace{14mu} {and}}\mspace{14mu} - {\sin \left( {2\pi \; f_{IF}\frac{T_{b}}{L}n} \right)}$

take the values from the sequences {+1,0,−1,0,+1, . . . } and{−1,0,+1,0,−1, . . . }, respectively. In a particular embodiment, f_(IF)is chosen to be equal to

${\frac{1}{4}\frac{L}{T_{b}}\left( {= {\frac{1}{4}f_{s}}} \right)},$

where

$f_{s} = {\frac{L}{T_{b}} = {LR}_{b}}$

is the sampling frequency of ADC. In this embodiment,

${{2\pi \; f_{IF}\frac{T_{b}}{L}n} = {{2\pi \frac{1}{4}\frac{L}{T_{b}}\frac{T_{b}}{L}n} = {\frac{\pi}{2}n}}},$

and, thus,

${{\cos \left( {2\pi \; f_{IF}\frac{T_{b}}{L}n} \right)}\mspace{14mu} {and}}\mspace{14mu} - {\sin \left( {2\pi \; f_{IF}\frac{T_{b}}{L}n} \right)}$

take the trivial values of +1,0,−1,0,+1,0, . . . , and −1,0,+1,0,−1, . .. respectively.

After multiplication of y_(IF)[n] by

${{\cos \left( {2\pi \; f_{IF}\frac{T_{b}}{L}n} \right)}\mspace{14mu} {and}}\mspace{14mu} - {\sin \left( {2\pi \; f_{IF}\frac{T_{b}}{L}n} \right)}$

the resulting signals 524 contain the desired baseband signal as well asits undesirable spectral components around 2f_(IF). These undesirablecomponents and any additional signals that may arise from out of bandnoise or interference from other communication channels are filtered bythe lowpass filters SRRC 510 and 520, p_(r)(t), which are chosen to bematched to the pulse shaping filter(s) at the transmitter side.

In the illustrated embodiment, the signals include preambles configuredto enable timing recover and frequency offset estimation. In someembodiments, only the signal on one channel, such as the in-phasechannel is needed for these functions. This signal is provided to module526 to recover a timing recovery value Δ and a frequency offset estimateΔf. The signals output by filters 520 and 521 are then delayed by Δ atmodules 511, and 512 respectively. Alter timing recovery, the signalsare down sampled by L at down-samplers 512 and 517, respectively.Frequency offset compensation is then performed using mixers 507 and518, respectively. In the in-phase components are multiplied 507 bycos(2 πΔfn) (522) and the quadrature components are multiplied 518 bysin(2 πΔfn) (525) using the value of Δf retrieved by module 526.

After this process, the signal 523 is a series of samples at the samplerate R 523 with in-phase and quadrature components. This signal isprovided to the demodulator 508 for demodulation, and subsequently tomodules for descrambling, deinterleaving, despreading, and decoding.

In some embodiments, the ADC 514 may comprise a single-hit ADC. Thesingle-bit ADC samples the signal and retains only the sign of thesignal. The amplitude the signal is completely ignored. Although thisreduces receiver sensitivity, this sampling scheme greatly reducescurrent consumption by eliminating the need for a variable gainamplifier (VGA) or automatic gain control (AGC) modules across theanalog and digital domains. The single-bit ADC further relaxesconstraints on the linearity of the amplifier. Although a single bit ADCwill introduce increased quantization errors than a multi-bit ADC, thiscan somewhat be countered by oversampling. Although a single-bit ADCeliminates all the information conveyed by the amplitude of the signal,it is suitable for applications using phase modulation schemes such aspi/2 DBPSK, BPSK, DBPSK, Double DBPSK, and higher order constantenvelope (or near constant envelope) versions of offset QPSK, such aFQPSK, and MIL-STD SOQPSK. When operated through a non-linear (hardlimited) channel, the BER performance of these higher-order waveforms isnot significantly affected in comparison to linear channels.

In packet based communications systems, such as the system describedwith respect to FIGS. 4 and 5 acquisition involves packet detection asone of the fast functions to be executed at the physical layer, sincethe receiver does not know a priori whether a packet is present, andwhere it exactly starts. Once a packet is detected, subsequentprocessing for time and frequency synchronization and demodulation canbe done, including frequency offset correction for the payload portion(beyond preamble). Hence, the remaining synchronization process isdependent on good packet detection performance. Generally, a sequence ofknown signals or symbols (usually called a preamble) is transmitted atthe beginning of a packet, and must be identified by the receiver inorder to detect a packet.

FIG. 6 illustrates an embodiment of a preamble structure fortransmission with packets in the system described with respect to FIG.5. The preamble 600 is transmitted before the header and data portionsof a packet. In one embodiment, the preamble bits are modulated usingπ/2-DBPSK modulation and are transmitted at the symbol rate. Thepreamble 600 is divided into three portions dedicated respectively todelay correlation 601, timing acquisition 602 (match filtering once apacket is asserted to be present after delay correlation), and frequencyoffset estimation 603.

The delay correlation portion 601 comprises a preamble having arepeating structure where groups of symbol values are repeated. Thesymbols of the preamble may comprises single bit symbols. In someembodiments, a delay correlation portion 601 may he less than or equalto 64 bits long, but still have a strong probability of detection andlow probability of false alarm detection. In the illustrated embodiment,the first portion 601 comprises 12 groups with 4 bits in each group thatare repeated. This preamble structure allows flexibility in delaycorrelation design. For example, delay correlation may be performedusing each group of 4 bits, or delay correlation may be used on multiplegroup repeats, such as 2 group repeats of 8 bits, or even 6 grouprepeats of 24 bits.

In the system of FIG. 5, packet acquisition and frequency offset areperformed by module 526 using portion 601. Correlation with a knownsequence 602, such as pseudorandom binary sequence, for example, anm-sequence is used for to provide symbol timing, and optionally, furthercorrelation for finer timing. In the illustrated embodiment, portion 602comprises a predetermined 30-bit m-sequence. The third portion 603comprises a sequence of alternating bits for frequency offsetestimation. In the illustrated embodiment, the portion 603 is 11 bitslong for a total preamble length of 90 bits, significantly shorter thanconventional system.

FIG. 7 illustrates a process for packet detection tuning recovery andfrequency offset estimation performed by the timing recovery module 526.In step 701 the signal energy is computed and delay correlation isperformed or the preamble portion 601. If the output of this processexceeds a threshold 702, a packet is detected and further processingoccurs. A coarse frequency offset estimation is performed in step 703using the preamble 600. The preamble is then derotated (corrected forthe coarse frequency offset) in step 704. The coarse-frequency correctedpreamble portion 602 is correlated with a known sequence 705 todetermine a peak and timing value. In some embodiments, further optionalprocessing 706 may take place for fine timing correction, in a typicalmanner known in the art.

Delay correlation can be used to detect the presence of a packet when aportion of the preamble of the packet is repeated. In the illustratedsystem, packet detection is based on correlation of the received signal601 with a delayed version of itself. In this embodiment, even when thenumber of samples over which delay correlation is performed isrelatively small, the all essentially desirable features of the (coarse)timing and frequency offset estimation statistics are preserved even foraccumulation lengths down to 1. Reducing the accumulation length haslittle effect even on some theoretical approximations of the detectionthreshold (although alternative threshold settings are preferred inimplementation). FIG. 8 depicts the signal processing performed at thereceiver in FIG. 5 during delay correlation.

The upper path in the block diagram computes delay correlation metric.M₂ whereas the lower path computes the energy of the signal M₁. Thesignal 804 comprises the preamble 601. The signal is delayed at arunning sum, taking account of the oversampling rate L 806, in module807. In the upper path, the signal is multiplied with conjugate 805 ofthe delayed version in mixer 801. A moving sum of these values 803 isaccumulated for the length of the preamble. In the illustratedparticular preamble 601, there are 11 groups of 4 symbols, so the sum isover 44*L samples. The magnitude of this amount 802 is used as the delaycorrelation metric M₂=a.

In the lower path, the energy of the samples 810 is added 811 with theenergy of the delayed samples 809. These results are also summed overthe length of the preamble 813 to generate an energy metric M₁. Thismetric is scaled 812 to produce a value b for comparison to the delaymetric a. In packet detection module 8008, if a>b then a counter isincremented. If the counter reaches a predetermined required wait value,a packet is detected. Otherwise, the counter is reset for future packetdetection. In some embodiments employing a single it ADC, a constantthreshold value may be used rattier than the energy threshold b.

Following delay correlation, a coarse estimate of time and frequencygiven a detected packet is available. A finer estimation of timesynchronization can be obtained by first frequency correcting subsequentpreamble portion 602 and performing a correlation with a referencem-sequence stored at the receiver. In the illustrated embodiment, thereference sequence is of length 31 and is the π/2-DBPSK modulatedup-sampled, and SRRC filtered equivalent for the bit pattern m0 . . .m30 602 that is part of the preamble after delay correlation sequence.In this embodiment, the correlation metric M₃ is given by,

     M₃? • |?indicates text missing or illegible when filed

where t_(k) is one of the 31 L=248 samples (upsampled length-31 sequenceis 31 L sample long) in the long reference sequence. The maximum pointgives the estimate of the time offset. In some embodiments, the maximumcan is also compared with a threshold to further prevent any falsealarm.

Returning to FIG. 3, after the demodulated symbols are descrambled anddeinterleaved, they are despread in module 314. In some embodiments,soft information in the signal may be combined b despreader module 314.In particular, this may be applied when the communications modulationsystem utilizes a system where the information exists only along onedimension, for example the in-quadrature component. For example, this isa property of occurs in

$\frac{\pi}{2} - {{DBPSK}.}$

As a result, it is possible straightforwardly combine thesoft-information prior to de-spreading, and only afterward performhard-demodulation; the hard-demodulated coded bits can be fed to a harddecoder 316. Using a matched filter 308, such a an SRRC filter, thissoft information exists even when a single-bit ADC is used as ADC 306.In alternative embodiments, the soft information can be used to performsoft-decoding in decoder 316.

An example configuration of a demodulator 508 fordifferentially-coherent encoded M-PSK is illustrated in FIG. 9. In thisfigure, for ease of illustration, only signal components are shown (i.e.the figure illustrates the noise-free equivalent). In the differentiallycoherent coded M-PSK scheme, information is encoded into phase shifts,which take values in the set

$\left\{ {{\frac{2\pi}{M}\left( {j - 1} \right)} + \Phi} \right\}_{j = 1}^{M}$

where Φ denotes the phase misalignment due to non-coherence. Asdiscussed above, the process may be employed using one dimension of thesignal, r(t). In the illustrated embodiment, the signal 905 is r(t)=

{{tilde over (r)}(t)e^(12πf) ^(v) ^(t)}. The signal 905 is delayed 902using the determined symbol delay to determine A cos(2 πf_(v)t+φ). Thisis then phase shifted 903 by an amount

$\Phi - \frac{\pi}{2}$

to derive the signal r_(D) ^(t)(t). In the upper path r(t) is multiplied909 with r_(D) ^(t)(t), and integrated 901 over the set of spreadsymbols to derive the combined soft despreading information for one ofthe signal components. In the lower path, r_(D) ^(t)(t) is phase shifted906 by

$\frac{\pi}{2}$

before multiplication 908 with r(t) and integration 907 to derive thecombined soft despreading information for the other component. Thedemodulator then can use the soft-despreading information in harddecoding maximum likelihood (ML) decision module 904 as illustrated tohard-demodulate the signal. In alternative embodiments, the haddemodulator block 904 may instead comprise a soft-decoder.

Some embodiments of the invention operate in communications environmentsemploy block FEC codewords, such as algebraic FEC codewords. Inparticular, certain embodiments operate on BCH codes. In suchenvironments, a packet comprises a plurality of codewords. In somecases, these codewords will have uncorrectable errors, resulting incorrupted packets. In some embodiments, the decoder detects if acodeword has a detectable but uncorrectable error, and if so, stopsdecoding the remainder of the packet. This process can potentiallysignificantly reduces baseband power consumption (60% asymptotically)associated with the decoder operation. FIG. 10 illustrates such amethod.

In step 1002, the receiver obtains a packet comprising a plurality ofcodewords. In step 1004, the decoder obtains a first codeword of thepacket, or in a repetition of the method, the next codeword of thepacket. During the decoding process, the decoder evaluates 1005 thecodeword to determine if the codeword contains a detectable butuncorrectable error. All of the detectable uncorrectable errors can befound, in one embodiment, by monitoring whether the Chien searcher findsfewer roots than the degree of the error locator polynomial. If thesyndrome s₁=0 then the coefficients of the error locator polynomialcannot he solved for, and decoding can be safely stopped and the packetis reported as corrupt 1007. There is no additional information inre-calculating syndromes post-error correction, and doing so onlyexpends power. If as many roots as the degree of the error locatorpolynomial turn out in the error locator field, then either correct orincorrect decoding 1006 has occurred (and the latter is undetectable).This process further improves the reliability of the system becausethere is a possibility that a residual error would be undetectable atthe MAC layer, in which case the MAC layer would forward the corruptedpayload to the application layer. Reducing the probability of a residualerror in a packet provided to the MAC layer reduces the number ofcorrupted payloads provided to the application layer. Additionally,reducing the number of corrupted packets provided to the MAC layerimproves the packet error rate seen by the MAC layer.

As used herein, the term module might describe a given unit offunctionality that can be performed in accordance with one or moreembodiments of the present invention. As used herein, a module might beimplemented utilizing any form of hardware, software, or a combinationthereof. For example, one or more processors, controllers, ASICs, PLAs,PALs, CPLDs, FPGAs, logical components, software routines or othermechanisms might be implemented to make up a module. In implementation,the various modules described herein might be implemented as discretemodules or the functions and features described can be shared in part orin total among one or more modules. In other words, as would be apparentto one of ordinary skill in the art after reading this description, thevarious features and functionality described herein may be implementedin any given application and can be implemented in one or more separateor shared modules in various combinations and permutations. Even thoughvarious features or elements of functionality may be individuallydescribed or claimed as separate modules, one of ordinary skill in theart will understand that these features and functionality can be sharedamong one or more common software and hardware elements, and suchdescription shall not require or imply that separate hardware orsoftware components are used to implement such features orfunctionality.

Where components or modules of the invention are implemented in whole orin part using software, in one embodiment, these software elements canbe implemented to operate with a computing or processing module capableof carrying out the functionality described with respect thereto. Onesuch example computing module is shown in FIG. 11. Various embodimentsare described in terms of this example-computing module 1100. Afterreading this description, it will become apparent to a person skilled inthe relevant art how to implement the invention using other computingmodules or architectures.

Referring now to FIG. 11, computing module 1100 may represent, forexample, computing or processing capabilities found within desktop,laptop and notebook computers; hand-held computing devices (PDA's, smartphones, cell phones, palmtops, etc.); mainframes, supercomputers,workstations or servers; or any other type of special-purpose orgeneral-purpose computing devices as may be desirable or appropriate fora given application or environment. Computing module 1100 might alsorepresent computing capabilities embedded within or otherwise availableto a given device. For example, a computing module might be found inother electronic devices such as, for example, digital cameras,navigation systems, cellular telephones, portable computing devices,modems, routers, WAPs, terminals and other electronic devices that mightinclude some form of processing capability.

Computing module 1100 might include for example, one or more processors,controllers, control modules, or other processing devices, such as aprocessor 1104. Processor 1104 might be implemented using ageneral-purpose or special-purpose processing engine such as, forexample, a microprocessor, controller, or other control logic. In theillustrated example, processor 1104 is connected to a bus 1102, althoughany communication medium can be used to facilitate interaction withother components of computing module 1100 or to communicate externally.

Computing module 1100 might also include one or more memory modules,simply referred to herein as main memory 1108. For example, preferablyrandom access memory (RAM) or other dynamic memory, might be used forstoring information and instructions to be executed by processor 1104.Main memory 1108 might also be used for storing temporary variables orother intermediate information during execution of instructions to beexecuted by processor 1104. Computing module 1100 might likewise includea read only memory (“ROM”) or other static storage device coupled to bus1102 for storing static information and instructions for processor 1104.

The computing module 1100 might also include one or more various formsof information storage mechanism 1110, which might include, for example,as media drive 1112 and a storage unit interface 1120. The media drive1112 might include a drive or other mechanism to support fixed orremovable storage media 1114. For example, a hard disk drive, a floppydisk drive, a magnetic tape drive, an optical disk drive, as CD or DVDdrive (R or RW), or other removable or fixed media drive might beprovided. Accordingly, storage media 1114 might include, for example, ahard disk, a floppy disk, magnetic tape, cartridge, optical disk, a CDor DVD, or other fixed or removable medium that is read by, written toor accessed by media drive 1112. As these examples illustrate, thestorage media 1114 can include a computer usable storage medium havingstored therein computer software or data.

In alternative embodiments, information storage mechanism 1110 mightinclude other similar instrumentalities for allowing computer programsor other instructions or data to he loaded into computing module 1100.Such instrumentalities might include, for example, a fixed or removablestorage unit 1122 and an interface 1120. Examples of such storage units1122 and interfaces 1120 can include a program cartridge and cartridgeinterface, a removable memory (for example, a flash memory or otherremovable memory module) and memory slot, as PCMCIA slot and card, andother fixed or removable storage units 1122 and interfaces 1120 thatallow software and data to be transferred from the storage unit 1122 tocomputing module 1100.

Computing module 1100 might also include a communications interface1124. Communications interface 1124 might be used to allow software anddata to be transferred between computing module 1100 and externaldevices. Examples of communications interface 1124 might include a modemor softmodem, a network interface (such as an Ethernet, networkinterface card, WiMedia, IEEE 802.XX or other interface), acommunications port (such as for example, a USB port, IR port, RS232port Bluetooth® interface, or other port), or other communicationsinterface. Software and data transferred via communications interface1124 might typically be carried on signals, which can he electronic,electromagnetic (which includes optical) or other signals capable ofbeing exchanged by a given communications interface 1124. These signalsmight be provided to communications interface 1124 via a channel 1128.This channel 1128 might carry signals and might be implemented using awired or wireless communication medium. Some examples of a channel mightinclude a phone line, a cellular link, an RF link, an optical link, anetwork interface, a local or wide area network, and other wired orwireless communications channels.

In this document, the terms “computer program medium” and “computerusable medium” are used to generally refer to media such as, forexample, memory 1108, storage unit 1120, media 1114, and channel 1128.These and other various forms of computer program media or computerusable media may be involved in carrying one or more sequences of one ormore instructions to a processing device for execution. Suchinstructions embodied on the medium, are generally referred to as“computer program code” or a “computer program product” (which may begrouped in the form of computer programs or other groupings). Whenexecuted, such instructions might enable the computing module 1100 toperform features or functions of the present invention as discussedherein.

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample only, and not of limitation. Likewise, the various diagrams maydepict an example architectural or other configuration for theinvention, which is done to aid in understanding the features andfunctionality that can be included in the invention. The invention isnot restricted to the illustrated example architectures orconfigurations, but the desired features can be implemented using avariety of alternative architectures and configurations. Indeed, it willbe apparent to one of skill in the art how alternative functional,logical or physical partitioning and configurations can be implementedto implement the desired features of the present invention. Also, amultitude of different constituent module names other than thosedepicted herein can be applied to the various partitions. Additionally,with regard to flow diagrams operational descriptions and method claims,the order in which the steps are presented herein shall not mandate thatvarious embodiments be implemented to perform the recited functionalityin the same order unless the context dictates otherwise.

Although the invention is described above in terms of various exemplaryembodiments and implementations, it should be understood that thevarious features, aspects and functionality described in one or more ofthe individual embodiments are not limited in their applicability to theparticular embodiment with which they are described, but instead can inapplied, alone or in various combinations, to one or more of the otherembodiments of the invention, whether or not such embodiments aredescribed and whether or not such features are presented as being a partof a described embodiment. Thus, the breadth and scope of the presentinvention should not be limited by any of the above-described exemplaryembodiments.

Terms and phrases used in this document, and variations thereof, unlessotherwise expressly stated, should be construed as open ended as opposedto limiting. As examples of the foregoing: the term “including” shouldbe read as meaning “including, without limitation” or the like; the term“example” is used to provide exemplary instances of the item indiscussion, not an exhaustive or limiting list thereof; the terms “a” or“an” should be read tis meaning “at least one,” “one or more” or thelike; and adjectives such as “conventional,” “traditional,” “normal,”“standard,” “known” and terms of similar meaning should not be construedas limiting the item described to a given time period or to an itemavailable as of a given time, but instead shown be read to encompassconventional, traditional, normal, or standard technologies that may beavailable or known now or at any time in the future. Likewise, wherethis document refers to technologies that would be apparent or known toone of ordinary skill in the art, such technologies encompass thoseapparent or known to the skilled artisan now or at any time in thefuture.

The presence of broadening words and phrases such as “one or more,” “atleast,” “but not limited to” or other like phrases in some instancesshall not be read to mean that the narrower case is intended or requiredin instances where such broadening phrases may be absent. The use of theterm “module” does not imply that the components or functionalitydescribed or claimed as part of the module are all configured in acommon package. Indeed, any or all of the various components of amodule, whether control logic or other components, can be combined in asingle package or separately maintained and can further be distributedin multiple groupings or packages or across multiple locations.

Additionally, the various embodiments set forth herein are described interms of exemplary block diagrams, flow charts and other illustrations.As will become apparent to one of ordinary skill in the art afterreading this document, the illustrated embodiments and their variousalternatives can be implemented without confinement to the illustratedexamples. For example, block diagrams and their accompanying descriptionshould not be construed as mandating a particular architecture orconfiguration.

1. A decoder module configured to perform the steps of: obtaining apacket comprising a plurality of codewords; determining if a firstcodeword of the packet contains a detectable correctable error; notdecoding subsequent codewords from the packet if the first codewordcontains an uncorrectable error; and decoding the first codeword anddetermining if a next codeword of the packet contains an correctableerror if the first codeword does not contain a detectable uncorrectableerror.
 2. The decoder module of claim 1, wherein the codewords of thepacket are from a predetermined algebraic forward error correction (FEC)code, and wherein the step of determining if a first codeword of thepacket contains a detectable uncorrectable error comprises; determiningan error locator polynomial for the first codeword; determining theroots of the error locator polynomial; determining that the firstcodeword contains a detectable uncorrectable error if the number ofdetermined roots of the error locator polynomial is less than the degreeof the error locator polynomial.
 3. The decoder module of claim 2,wherein the step of determining the roots of the error locatorpolynomial is performed using a Chien search.
 4. A method, comprising:obtaining a packet comprising a plurality of codewords; determining if afirst codeword of the packet contains a detectable uncorrectable error;not decoding subsequent codewords from the packet if the first codewordcontains an uncorrectable error; and decoding the first codeword anddetermining if a next codeword of the packet contains an uncorrectableerror if the first codeword does not contain a detectable uncorrectableerror.
 5. The method of claim 4, wherein the codewords of the packet arefrom a predetermined algebraic forward error correction (FEC) code, andwherein the step of determining if a first codeword of the packetcontains a detectable uncorrectable error comprises: determining anerror locator polynomial for the first codeword; determining the rootsof the error locator polynomial; determining that the first codewordcontains a detectable uncorrectable error if the number of determinedroots of the error locator polynomial is less than the degree of theerror locator polynomial.
 6. The method of claim 5, wherein the step ofdetermining the roots of the error locator polynomial is performed usinga Chien search.